ASIC Design Verification Engineer | UVM | Exp. 8+ years

Join our team as a ASIC Design Verification Engineer, where you will define, design, and verify ASIC and subsystems for Cisco platforms. You will architect and develop DV infrastructure, develop test plans, and ensure RTL quality. Ideal candidates have significant ASIC verification experience and expertise in UVM/System Verilog.

• Seniority: Mid Level
• Languages: English