ASIC Design Verification Engineer || Verilog, UVM, Testbench | Emulation || Exp 7+ years

We are looking for an ASIC Design Verification Engineer to develop and execute verification strategies for complex hardware designs, focusing on emulation platforms. You will collaborate with multidisciplinary teams to ensure verification accuracy and performance. Ideal candidates have significant experience in ASIC design verification and strong expertise in UVM or OVM.

• Seniority: Mid Level
• Languages: English