ASIC Design Verification Engineer || Verilog, UVM, Testbench | Simulation || Exp 7+ years

We are seeking an ASIC Design Verification Engineer to develop and execute verification strategies for complex hardware designs. You will collaborate with multidisciplinary teams, focusing on emulation platforms and simulation tools. Ideal candidates have significant experience in ASIC design verification and strong expertise in UVM or OVM.

• Seniority: Mid Level
• Languages: English