ASIC DFT DV Engineer || System Verilog, UVM || JTAG, MBIST || Exp : 8+ years

Seeking an ASIC DFT DV Engineer to drive high-quality DFT verification and test planning for advanced networking hardware. Collaborate with RTL and physical design teams, develop test benches, and support ATE screening and diagnostics. Ideal for candidates with extensive experience in System Verilog, DFT, and test strategy.

• Seniority: Mid Level
• Languages: English