ASIC Design Verification (DV) Manager

We are currently hiring a ASIC Design Verification (DV) Manager to architect and develop block-level verification environments for ASICs, focusing on SystemVerilog and UVM methodologies. The role involves defining and delivering verification suites, and collaborating with logic designers and software developers. Ideal for candidates with ASIC verification experience and strong problem-solving skills.

• Seniority: Senior Level
• Languages: English