ASIC Front-end Design engineer

HPE

Bengaluru

Full-Time

0-3 Years experience

Description

We are recruiting an ASIC Front-end Design Engineer to define and architect high-performance blocks for advanced networking ASICs. You will collaborate with system design teams and contribute to high-speed, complex system development. Ideal candidates possess strong Verilog RTL coding skills and experience in ASIC design for networking protocols.

Eligibility Criteria

Seniority: Mid Level
Languages: English

About HPE

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